Achronix Speedster22i 10G/40G/100G Ethernet Manual de usuario

UG029, September 6, 2013 1 Speedster22i 10/40/100 Gigabit Ethernet User Guide UG029 – September 6, 2013

10 UG029, September 6, 2013 Functional Description Figure 1: 10/40/100 Gigabit Ethernet MAC Block Diagram On the FPGA Fabric interface side, the

100 UG029, September 6, 2013 4 22[7:0] 23[0:0] RXEQ_FINE_RUN_MASK RW 1FD Equalization calibration fine mode variable control mask. Each bit co

UG029, September 6, 2013 101 off frequency 4 2B[5:3] RXEQ_DFEPSTAPF3DB_LUP0 RW 7 Equalization calibration lookup table code 0 - Pulse-shaping DF

102 UG029, September 6, 2013 Statistics Data Registers Overview The 10 / 40 / 100 Gigabit Ethernet Channelized MAC Core provides a set of signals p

UG029, September 6, 2013 103 Receive Statistics Vector The Channelized MAC Core provides a Receive Statistics Vector per segment that support the stat

104 UG029, September 6, 2013 Table 66 – Receive Statistics Vector IETF RMON MIB Objects Object Description etherStatsDropEvents Counts the number

UG029, September 6, 2013 105 Transmit Statistics Vector The Channelized MAC Core provides a Transmit Statistics Vector per segment that support the st

106 UG029, September 6, 2013 the destination address set to '1' but not the broadcast address (all bits set to '1'). ifOutBroad

UG029, September 6, 2013 107 References  IEEE 802.3-2005  IEEE 802.3ae  RFC2665, Definitions of Managed Objects for the Ethernet-like Interface

108 UG029, September 6, 2013 Revision History The following table shows the revision history for this document. Date Version Revisions 4/26/2013 1.

UG029, September 6, 2013 11

12 UG029, September 6, 2013 Interface Signal List ref_clkreset_ff_rx_clk_n[2:0]reset_ff_tx_clk_n[2:0]reset_nreset_ref_clk_nalign_done[2:0]block_loc

UG029, September 6, 2013 13 Interface Signal Descriptions Global Signals Table 1 – Global Signals Signal Name Mode Description ref_clk In Reference Cl

14 UG029, September 6, 2013 000110: ff_rx_data[47:0] is valid 000111: ff_rx_data[55:0] is valid 001000: ff_rx_data[63:0] is valid (40/100G only) 00

UG029, September 6, 2013 15 SFD of the frame. Valid with ff_rx_sop. The receive timestamp ff_rx_ts[31:0] can be mapped to any segment of FIFO group 0

16 UG029, September 6, 2013 111111: ff_tx_data[503:0] is valid (100G only) ff_tx_err[11:0] In Transmit Frame Error per segment. Asserted with the

UG029, September 6, 2013 17 10 – Slumber Power State (P1) - PLL is enabled. CDR and Driver are disabled. Increased power consumption 01 – Doze Power

18 UG029, September 6, 2013 ff_tx_pfc_ack[11:0] Out Per segment Transmit Flow Control Acknowledge. Each segment provides an ACK back to the applic

UG029, September 6, 2013 19 completed thru SBUS. During write it is valid for one cycle to indicate the end of the transfer. This is asserted for 4-cy

2 UG029, September 6, 2013 Copyright Info Copyright © 2013 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademar

20 UG029, September 6, 2013 counter (FRC). Used for timestamping. The value typically expresses nanoseconds within the current one second interval,

UG029, September 6, 2013 21 Implementation with ACE Software/Hardware Requirements The ACE software suite has the following system requirements:  P

22 UG029, September 6, 2013 Figure 3: 10/40/100G Ethernet MAC IP Wizard Additionally, the user will need to select the placement of the core. Th

UG029, September 6, 2013 23 Figure 4: Generate IP Design Files dialog box

24 UG029, September 6, 2013 FPGA Fabric Interface The fabric interface is the primary interface for the user to connect his design to the 10/40/100

UG029, September 6, 2013 25 Figure 5: Simulation Flow Software simulation can be done pre-tool chain at the functional RTL level, post-synthesis at

26 UG029, September 6, 2013 Clock Distribution The clock frequency of the SerDes interface depends on the selected SerDes datapath width (synthesis

UG029, September 6, 2013 27 Figure 7: Example implementation for the FIFO clock and reset multiplexers

28 UG029, September 6, 2013 Reset Considerations MAC Soft Reset When the MAC control register (COMMAND_CONFIG) reset bit is written, the following

UG029, September 6, 2013 29 Fabric FIFO Interface Overview The following table shows the segment definition and datapath bit assignments for each conf

UG029, September 6, 2013 3 Table of Contents Copyright Info ...

30 UG029, September 6, 2013 Transmit FIFO Interface Block Diagram Figure 8: Transmit FIFO Interface Block Diagram

UG029, September 6, 2013 31 Receive FIFO Interface Block Diagram Figure 9: Receive FIFO Interface Block Diagram

32 UG029, September 6, 2013 Credit Handling The following figure provides an overview of the credit based application interface. Figure 10: Credi

UG029, September 6, 2013 33 Transmit Direction: Application to FIFO On transmit, it is the responsibility of the application to monitor the ff_tx_rdy

34 UG029, September 6, 2013 000001 ff_tx_data[7:0) ff_rx_data[7:0) 000010 ff_tx_data[15:0] ff_rx_data[15:0] 000011 ff_tx_data[23:0] ff_rx_data[23:0

UG029, September 6, 2013 35 Table 19 – 10G Transmit/Receive FIFO Interface Word Modulo Definition ff_tx_mod[5:0] ff_rx_mod[5:0] Valid Bytes 000000 ff_

36 UG029, September 6, 2013 Table 20 – FIFO Interface Frame Format Byte Number Field 0 to 5 Destination MAC Address 6 to 11 Source MAC Address 12 t

UG029, September 6, 2013 37 FIFO Interface Transmit Operation The application layer drives data and controls based on the configuration mode. Note tha

38 UG029, September 6, 2013 sys_clkff_tx_wren[0]ff_tx_data[511:0]ff_tx_mod[5:0]ff_tx_sop[0]ff_tx_eop[0]ff_tx_err[0] Figure 12: FIFO Transmit Interf

UG029, September 6, 2013 39 The transmit FIFO interface is protected against the following invalid signaling conditions:  Missing SOP: All ff_tx_wre

4 UG029, September 6, 2013 Fabric FIFO Interface... 29 Overview

40 UG029, September 6, 2013 sys_clkff_rx_data[511:0]ff_rx_sop[0]ff_rx_eop[0]ff_rx_mod[5:0]ff_rx_err[0]ff_rx_vlan[1:0]ff_rx_err_stat[23:0]ff_rx_dval

UG029, September 6, 2013 41 When an Ethernet frame is received with an error, the frame is transmitted to the user application with the frame error si

42 UG029, September 6, 2013 sys_clkff_rx_data[511:0]ff_rx_sop[0]ff_rx_eop[0]ff_rx_mod[5:0]ff_rx_err[0]ff_rx_vlan[1:0]ff_rx_err_stat[23:0]ff_rx_dval

UG029, September 6, 2013 43 Table 22 – Frame Status Word Bits Bit # Name Description 0 LENGTH_ERROR Set to ‘1’ if the frame has an invalid length. Thi

44 UG029, September 6, 2013 The following figure shows the relationship of the configuration values and their respective signals and levels above a

UG029, September 6, 2013 45 Table 23 – FIFO Sections Configuration Register Behavior RX_FIFO_SECTIONS[15:0] Section Available: Legacy purpose only. No

46 UG029, September 6, 2013 Table 24 – Pause Frame Format (values in hex) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 55 55 55 55 55 55 55 D5 01 80 C2 00 00 0

UG029, September 6, 2013 47 Transmit Pause/PFC Operation In transmit direction, for each of the 12 segments, an 8-bit input vector (ff_tx_pfc_xoff<

48 UG029, September 6, 2013 A configuration option (see COMMAND_CONFIG(PAUSE_IGNORE)) allows ignoring pause frames, preventing the transmitter from

UG029, September 6, 2013 49 Serial Bus Interface Overview The Serial Bus (SBUS) Slave module is a low pin count serial interface for data transfer be

UG029, September 6, 2013 5 Transmit Timestamping ...

50 UG029, September 6, 2013 A0,1'b0 A2,A1A16,A15sbus_clki_sbus_reqi_sbus_data[1:0]o_sbus_acko_sbus_data[1:0]D1,D0 D3,D2 D31,D30D29,D28 Figure

UG029, September 6, 2013 51 PMA Management Interface Power State Descriptions The PMA supports the following 5 power States. Power state transition

52 UG029, September 6, 2013 Table 28 – Overview of PMA Behavior During the Various Power States IO Pin Signal P0 P0s P1 P2 Power Down Hard Re

UG029, September 6, 2013 53 Power State Sequencing The following diagram demonstrates the allowed power state transitions for the PMA: Figure 25: P

54 UG029, September 6, 2013 Auto-Negotiation Overview Each PCS layer implements an auto-negotiation function that allows the local device to advert

UG029, September 6, 2013 55 Control Register Bits (KXAN_CONTROL) through Next page Ability Register Bits (AN_XNP / LP_AN_XNP) for details). Usage Afte

56 UG029, September 6, 2013 control bit has been set the AN_XNP registers become writeable. When NextPage control is disabled (bit13=0), a so-calle

UG029, September 6, 2013 57 As soon as the PCS has established the link (block_lock asserted and align_done set accordingly for 40G and 100G mode of o

58 UG029, September 6, 2013 IEEE 1588 Timestamping The 10 / 40 / 100 Gigabit Ethernet Channelized MAC Core supports IEEE 1588 Receive and Transmit

UG029, September 6, 2013 59 Registers MAC & PCS Configuration Registers MAC & PCS Register Overview The MAC & PCS register address space i

6 UG029, September 6, 2013 References ... 107

60 UG029, September 6, 2013 Table 31 – Core Register Map – Global Registers Address Page# Description 10G 40G 100G 0x3000 12 Core Configuration Re

UG029, September 6, 2013 61 Channelized MAC Registers The Channelized MAC Registers are located on pages 0 through 11. Each segment has its own set of

62 UG029, September 6, 2013 384-bit). 9 24 RX_FIFO_ALMOST_F_E RO 15:0: RX FIFO almost empty threshold 31:16: RX FIFO almost full threshold Read

UG029, September 6, 2013 63 20 50 CREDIT_REG RO 7:0: Current credit register value (for debug purpose only). Bits 31:8 are unused and always set to ‘0

64 UG029, September 6, 2013 pause condition still exists. 29 74 RX_PAUSE_STATUS RO 7:0: Status bit for software to read the pause status. One bit f

UG029, September 6, 2013 65 58 E8 ifInMulticastPkts RO See Received Statistics Vector – IETF MIB(MIB-II) Objects" 60 F0 ifInBroadcastPkts RO See

66 UG029, September 6, 2013 110 1B8 aCBFCPAUSEFramesTransmitted_4 RO See Transmit Statistics Vector – IEEE 802.3 oMacEntity and oPauseEntity Manage

UG029, September 6, 2013 67 Mode. See “ 10G MAC SGMII PCS Register Map” on page 71. 224-255 380 -3fc reserved R(W) Note: The PCS registers are 32 reg

68 UG029, September 6, 2013 7 PAUSE_FWD Terminate / Forward Pause Frames. If set to '1', pause frames are forwarded to the user applicati

UG029, September 6, 2013 69 17 NO_LGTH_CHECK Disable Payload Length Check. If set to ‘0’ (Reset value), the Core checks the frame's payload lengt

UG029, September 6, 2013 7 Table of Figures Figure 1: 10/40/100 Gigabit Ethernet MAC Block Diagram ...

70 UG029, September 6, 2013 STATUS Register Bit Definitions Table 36 – STATUS Register Description Bit# Bit Name Type Description 0 RX_LOC_FAULT RO

UG029, September 6, 2013 71 10G MAC SGMII PCS Register Map When operating in 10G mode of operation, the 10G MAC can implement a configurable 10/100/10

72 UG029, September 6, 2013 5 314 PARTNER_ABILITY RO Received ability from remote device after auto-negotiation has completed. Depending on the mod

UG029, September 6, 2013 73 1000Base-X/SGMII PCS Registers Description Table 37 – (SGMII PCS) CONTROL Register Description Bit(s) Name Type Descript

74 UG029, September 6, 2013 4 Remote Fault RO Read Only Bit always set to ‘0’. The PCS does not implement a PHY specific remote fault detection opt

UG029, September 6, 2013 75 the bit in the device ability advertisement register is not relevant to the operation of the autonegotiation function. The

76 UG029, September 6, 2013 Table 42 – (SGMII PCS) IF_MODE Register Description Bit(s) Name Type Description 0 SGMII_ENA RW SGMII Mode Enable. Wh

UG029, September 6, 2013 77 Global Registers Core Configuration Registers The Core Configuration Registers are located on register page 12 (0x3000). T

78 UG029, September 6, 2013 6 18 TS_CTL_SEG RW 3:0: Timestamping support control (1 bit per segment). 0: no support for timestamping

UG029, September 6, 2013 79 2 08 VLAN_TPID_2 RW 15:0: VLAN Tag TPID 2. Bits 31:16 are unused and always set to ‘0’. 0x8100 3 0C VLAN_TPID_3 RW 15:0: V

8 UG029, September 6, 2013 Overview The hardened 10/40/100 Gigabit Ethernet controller available in Achronix Speedster22i FPGAs provides a flexib

80 UG029, September 6, 2013 Table 45 – PCS Register Map – General PCS Information Reg# Add. (hex) Register Name Type Description Reset 0 00 CONTROL

UG029, September 6, 2013 81 5 14 DEVICES IN PKG1 RO 15:7: Reserved 6: TC present 5: DTE XS present 4: PHY XS present 3: PCS present (default: 1) 2: WI

82 UG029, September 6, 2013 Table 46 – PCS Register Map – 10G/40G/100GBASE-PCS Registers Reg# Add. (hex) Register Name Type Description Reset 32 80

UG029, September 6, 2013 83 43 AC 10/40/100G BASE-R TEST ERR CNT ROR Test-pattern error counter. (NR) 0 44 B0 BER HIGH ORDER CNT RO 15:0: Bits 21:6 of

84 UG029, September 6, 2013 53 D4 MULTI-LANE ALIGN STATUS 4 RO 15:12: Reserved 11: Lane 19 alignment marker lock 10: Lane 18 alignment marker lock

UG029, September 6, 2013 85 103 19C BIP ERR CNT LANE 13 ROR 15:0: BIP error counter lane 13 (NR) Note: Bits 15:0 are reserved for 40GBASE-R. 0 104 1A0

86 UG029, September 6, 2013 123 1EC LANE MAP 13 RO 4:0: Lane mapping register for PCS lane 13 15:5: reserved Note: Bits 15:0 are reserved for 40GBA

UG029, September 6, 2013 87 Auto-Negotiation Registers The Auto-Negotiation Registers are located on page 28. Each segment has its own set of 16 auto-

88 UG029, September 6, 2013 ABILITY_2 Bit 0 is the ability word bit 32, bit 15 is the ability word bit 47. 14 KXAN_REM_ ABILITY_0 RO Received abili

UG029, September 6, 2013 89 Control Register Bits (KXAN_CONTROL) The control register controls the operation of the autonegotiation function. Table 4

UG029, September 6, 2013 9  Each PCS layer implements auto-negotiation, but does not include Parallel Detection. Parallel Detection must be implemen

90 UG029, September 6, 2013 9 Parallel Detection Fault Error with parallel detection. When the remote device does not support autonegotiation the a

UG029, September 6, 2013 91 Ethernet. Following are the technology ability field encoding: Bit-15 to Bit-11 are reserved. Bit-10: 100GBASE-CR10 Bit-9:

92 UG029, September 6, 2013 14 Acknowledge Acknowledge (Ack) is used by the auto-negotiation function to indicate that a device has successfully re

UG029, September 6, 2013 93 PMA Registers The PMA memory contains control registers which can be grouped into two main categories:  PMA Transmitt

94 UG029, September 6, 2013 TX/RX Lane Receive Equalization Registers Table 58 – TX/RX Lane Receive Equalizer Control Registers Reg Pg. (hex) Reg

UG029, September 6, 2013 95 -4'b0000: +0mVpeak -4'b0001: +9mVpeak ... -4'b0110: +46mVpeak -4'b0111: +53mVpeak -4'b1000:

96 UG029, September 6, 2013 Common/Synth Lane Receive Equalization Registers Table 59 – Common/Synth Lane Receive Equalizer Control Registers Reg

UG029, September 6, 2013 97 0 17[4:3] TXDRV_SLEW RW 0 TX driver Slew Rate control: 00 - 31ps 01 - 33ps 10 - 68ps 11 - 170ps 0 17[2:0] TXDRV_LEVN

98 UG029, September 6, 2013 is not used if PCIEMODE_SEL=0. 4 1A[5:4] CMNTXPIPE_TXDRVSLEW_GEN3 RW 0 TX IO driver slew-rate look-up table entry

UG029, September 6, 2013 99 Common/Synth Lane Adaptive Equalizer Registers Table 63 – Table 6-14: Common/Synth Lane Adaptive Equalizer FSM Registers