Achronix Speedster22i Pin Connections and Power Sequencing Manual de usuario descargar pdf (Pagina 7)

UG042, August 19, 2014

feature is used. NOT Available for HD1000.

other devices, connect directly to

observation point for error.

CONFIG_SCRUBBING_ENABLE

CFG

Input

Enables SCRUB feature for SEU mitigation in the configuration

memory. NOT Available for HD1000.

For the HD1000 tie this pin to GND. For

other devices, connect this pin directly to

the configuration controller.

CONFIG_SCRUB_SINGLE_ERR

CFG

Output

Indicates the presence of a single error when the SCRUB

feature is used. NOT Available for HD1000.

For the HD1000, leave unconnected. For

other devices, connect directly to

observation point for error.

General Purpose I/O Interface

RCOMP_TERM_B

[00,01,02,10,11,12,20,21,22,

30, 31,32,40,41,42,50,51,52]

BWN, BWC,

BWS, BES,

BEC, BEN

Input

Termination resistor input for dynamic drive compensation

for PVT and aging.

Terminate to GND through a changeable /

swappable resistor that will provide the

correct termination. Currently a 200Ω +/-

1% resistor is being used internally.

RCOMP_DRV_B

[00,01,02,10,11,12,20,21,22,

30, 31,32,40,41,42,50,51,52]

BWN, BWC,

BWS, BES,

BEC, BEN

Input

Drive resistor input for dynamic drive compensation for PVT

and aging.

Terminate to GND through a changeable /

swappable resistor that will provide the

correct drive strength. Currently a 25Ω +/-

1% resistor is being used internally.

PAD_[WS/WC/WN/ES/EC/EN]_BYTEIO

[12:0]DQ[9:0]

BWN, BWC,

BWS, BES,

BEC, BEN

Input /

Output

A group of 13 byte lanes. Each byte lane has 12 bits; 10 of

these 12 bits are used as data for memory interface

applications. Alternatively, these I/Os could be set for Single

Ended, Differential, LVCMOS, *STL and LVDS modes.

Unused I/Os can be left unconnected.

PAD_[WS/WC/WN/ES/EC/EN]_BYTEIO

[12:0]DQS

BWN, BWC,

BWS, BES,

BEC, BEN

Input /

Output

A group of 13 byte lanes. Each byte lane has 12 bits; the 11th

bit carries a synchronous strobe signal (positive polarity

differential clock) for referencing DQ[9:0] in each of the byte

lanes. Alternatively, these I/Os could be set for Single Ended,

Differential, LVCMOS, *STL and LVDS modes.

Unused I/Os can be left unconnected.

PAD_[WS/WC/WN/ES/EC/EN]_BYTEIO

[12:0]DQSN

BWN, BWC,

BWS, BES,

BEC, BEN

Input /

Output

A group of 13 byte lanes. Each byte lane has 12 bits; the 12th

bit carries a synchronous strobe signal (negative polarity

differential clock) for referencing DQ[9:0] in each of the byte

lanes. Alternatively, these I/Os could be set for Single Ended,

Differential, LVCMOS, *STL and LVDS modes.

Unused I/Os can be left unconnected.

Clock I/O Interface

RCOMP_TERM_CLK_BANK_[NW/SW/S

E/NE]

CB0, CB1,

CB2, CB3

Input

Termination resistor input for dynamic drive compensation

for PVT and aging.

Terminate to GND through a changeable /

swappable resistor that will provide the

correct termination. Currently a 200Ω +/-

1% resistor is being used internally.

RCOMP_DRV_CLK_BANK_[NW/SW/SE

/NE]

CB0, CB1,

CB2, CB3

Input

Drive resistor input for dynamic drive compensation for PVT

and aging.

Terminate to GND through a changeable /

swappable resistor that will provide the

correct drive strength. Currently a 25Ω +/-

1% resistor is being used internally.

PAD[5:0]_CLK_BANK_[NW/SW/SE/NE]

CB0, CB1,

CB2, CB3

Input /

Output

A group of six clock buffers that can be used either as three

differential I/Os or six single‐ended I/Os. If these I/Os are not

used as clock buffers, they can be used as generic inputs or

outputs.

Unused I/Os can be left unconnected.

1 2 3 4 5 6 7 8 9 10 11 12 13

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Achronix Speedster22i Pin Connections and Power Sequencing Manual de usuario Pagina 7

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