Achronix Speedster22i Memory PHY Manual de usuario descargar pdf (Pagina 7)

UG043, April 26, 2014

DDR PHY

Organization and Interfaces

Figure 4 provides a block diagram view of how the DDR PHY is organized, and how it

interfaces with other components of the memory interface sub-system. As shown, a PLL

input clock and an external reset are supplied to the DDR PHY, which can communicate with

3 separate interfaces: an external DDR memory, and based on the user’s implementation,

either the hard DDR controller in the IO ring or a soft DDR controller in the FPGA fabric. The

PHY needs to select between using the DDR controller vs communicating with a controller in

the FPGA fabric. This is done through a user-specified parameter. There are other parameters

as well to help select features and functionality in the DDR PHY.

Table 1 provides the port list for the FPGA internal interface, while Table 2 provides the port

list for the external DDR memory interface. Table 3 provides a parameter list to highlight the

available modes and options.

Speedster22i

ACX_PLL

clk

DDRxN

PHY

External

DDR Memory

DDRxN

Hard

Controller

DDRxN

Soft

Controller

Communication

with Application

Interface in Fabric

Communication

with Application

Interface in Fabric

IO Ring

Fabric

DDR PHY – Soft

Controller Interface

DDR PHY – Hard

Controller Interface

DDR PHY –

External DDR

Memory Interface

reset_n

Figure 4: DDR PHY Organization and Interfaces

1 2 3 4 5 6 7 8 9 10 11 12 ... 19 20

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