Achronix ACE Version 5.0 Manual de usuario Pagina 239
- Pagina / 389
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Projects Chapter 3. Concepts
Project File
Projects are persisted in project files (.acxprj file extension) created automatically by the tool whenever a
project is saved. A project file is actually just a Tcl script supporting only a defined subset of Tcl commands.
Users can edit project files manually and then load them into the tool to use as a script or for running
regressions.
In the GUI, loaded project file contents are displayed in a tree structure in the Projects view. Project file
contents may also be viewed in a text editor in the GUI by double-clicking on the project name in the
Projects view (example file contents shown below):
=======================================================
# proj2
# AUTOMATICALLY GENERATED FILE
# MAY BE OVERWRITTEN AT ANY TIME DURING USE OF TOOL
# Netlist Files
add_project_netlist -project proj2 "C:/test_projects/proj2/top.vma"
# Constraint Files
add_project_constraints -project proj2 "C:/test_projects/proj2/clock_mode2.sdc"
add_project_constraints -project proj2 "C:/test_projects/proj2/clock_mode1.sdc"
# Implementations
# impl_1
create_impl -project proj2 impl_1
set_impl_option -project proj2 -impl impl_1 partname ACSPD60-FBGA1892
set_impl_option -project proj2 -impl impl_1 speed_grade "standard"
set_impl_option -project proj2 -impl impl_1 core_voltage "1.00"
enable_project_constraints -project proj2 -impl impl_1 "C:/test_projects/proj2/clock_mode2.sdc"
disable_project_constraints -project proj2 -impl impl_1 "C:/test_projects/proj2/clock_mode1.sdc"
# impl_2
create_impl -project proj2 impl_2
set_impl_option -project proj2 -impl impl_2 partname ACSPD60-FBGA1892
set_impl_option -project proj2 -impl impl_2 speed_grade "standard"
set_impl_option -project proj2 -impl impl_2 core_voltage "0.95"
enable_project_constraints -project proj2 -impl impl_2 "C:/test_projects/proj2/clock_mode2.sdc"
enable_project_constraints -project proj2 -impl impl_2 "C:/test_projects/proj2/clock_mode1.sdc"
# impl_3
create_impl -project proj2 impl_3
set_impl_option -project proj2 -impl impl_3 partname ACSPD60-FBGA1892
set_impl_option -project proj2 -impl impl_3 speed_grade "standard"
set_impl_option -project proj2 -impl impl_3 core_voltage "0.95"
disable_project_constraints -project proj2 -impl impl_3 "C:/test_projects/proj2/clock_mode2.sdc"
disable_project_constraints -project proj2 -impl impl_3 "C:/test_projects/proj2/clock_mode1.sdc"
# End of file
=======================================================
Source Files
A project contains source files used as inputs to the ACE flow. There are two types of source files:
• Synthesized netlist files
• SDC/PDC constraints files
In the GUI, source files may be browsed in the Projects view and viewed in the built-in text editor by double
clicking on the file name in the Projects view.
IP Configurations
ACE provides GUI support to ease configuration of the most complicated embedded IP in Achronix FPGAs.
The data files used by the IP Configuration Editors (files with the .acxip extension) may optionally be
227 http://www.achronix.com UG001 Rev. 5.0 - 5th December 2012
- ACE User Guide 1
- Copyright Info 2
- Contents 3
- About This Guide 13
- Related Documents 13
- Getting Started 14
- ACE Quickstart Tutorial 15
- Concepts 16
- Text Editor 18
- HTML Report Browser 19
- Basic PLL Configuration Editor 32
- BRAM Configuration Editor 35
- DDR3 Configuration Editor 40
- Ethernet Configuration Editor 51
- FIFO Configuration Editor 55
- Interrupt Settings Page 72
- LRAM Configuration Editor 78
- LRAM FIFO Configuration Editor 81
- Memory Map Page 88
- ROM Configuration Editor 97
- SerDes Configuration Editor 100
- Editors Chapter 3. Concepts 102
- Channel Bonding Page 118
- VCD Waveform Editor 126
- Fast views 129
- Projects View 130
- Flow View 132
- Options View 134
- Multiprocess View 141
- Tcl Console View 147
- Search View 148
- Selection View 152
- Views Chapter 3. Concepts 155
- Figure 3.74: Selection View 155
- Critical Paths View 156
- Critical Path Diagram View 160
- Package View 164
- IO Assignment View 168
- Clock Regions View 172
- Netlist Browser View 174
- Placement Regions View 177
- Outline View 180
- IP Libraries View 181
- IP Diagram View 182
- IP Problems View 184
- Download View 186
- ”net192.168.100.101” 187
- Create Project Dialog 188
- Load Project Dialog 189
- Create Implementation Dialog 190
- Restore Implementation Dialog 191
- Save Implementation Dialog 192
- Create a New Text File Dialog 194
- Add Source Files Dialog 195
- Save Placement Dialog 197
- Save Script File Dialog 199
- New IP Configuration Dialog 200
- Configure Selected IOs Dialog 203
- Configure Table Columns Dialog 207
- Search Filter Builder Dialog 211
- Save Placement Regions Dialog 215
- Toolbars 216
- Preferences 217
- Floorplanner view 220
- IP Diagram Preference Page 225
- Package View Preference Page 230
- Text Editors Preference Page 234
- Projects 237
- Project File 239
- Source Files 239
- IP Configurations 239
- Output Files 240
- Log Files 240
- Flow Steps 242
- Flow Status 242
- Clock Report 243
- Utilization Report 243
- Pin Assignment Report 243
- Timing Report 244
- I/O Timing Report 245
- Routing Report 245
- Power Dissipation Report 245
- Multiprocess Summary Report 245
- Advanced Concepts 247
- Running ACE 248
- Working With Perspectives 249
- Opening Views 250
- Moving and Docking Views 250
- Rearranging Tabbed Views 250
- Creating Fast Views 251
- Tiling Editors 251
- Maximizing a View or Editor 251
- Creating Projects 252
- Loading Projects 252
- Removing Projects 252
- Saving Projects 252
- Adding Source Files 254
- Removing Source Files 255
- Creating Implementations 255
- Saving Implementations 256
- Restoring Implementations 256
- Copying Implementations 257
- Removing Implementations 257
- Running the Flow 259
- Place and Route Steps 260
- Design Completion Steps 260
- FPGA Programming Steps 261
- 2 5035008 263
- Using the Tcl Console 267
- Command Help 268
- Text Limit 269
- Clearing the Console 269
- Viewing the ACE Log File 270
- Object Type Prefixes 270
- Creating an IP Configuration 271
- Setting the IP Configuration 272
- Viewing the Floorplanner 273
- Selecting Objects 274
- Deselecting Objects 274
- Toggling Mouse Tools 275
- Filtering the View 275
- Getting Object Tooltips 275
- Viewing Object Labels 276
- Viewing the Package Layout 277
- Pre-Placing a Design 281
- Removing Placement 283
- Analyzing Critical Paths 284
- Zooming to Critical Paths 286
- Using Critical Path Diagrams 286
- Intermediate Nodes 290
- Managing I/Os 294
- Running the SnapShot Debugger 295
- Using the SnapShot Macro 297
- VHDL Instantiation: 300
- Setting Up the Scan Chain 302
- Entering a Trigger Pattern 302
- Configuring Test Stimulus 303
- Setting Triggering Range 304
- Configuring the Samples 304
- Collecting Samples 304
- Batch Mode 305
- Playing a STAPL File 306
- Optimizing a Design 307
- Placement Region Preferences 309
- Deleting Placement Regions 313
- Tcl Command Reference 314
- Usage Notes: 349
- Revision History 385
- Version 4.2.0: 387
- Version 3.2.0: 388
Relacionado con productos y manuales para Hardware De La Computadora Achronix ACE Version 5.0
Hardware De La Computadora Achronix Speedster22i Pin Connections and Power Sequencing Manual de usuario
(13 paginas)
(13 paginas)
Hardware De La Computadora Achronix Speedster22i Clock and Reset Networks Manual de usuario
(28 paginas)
(28 paginas)
Hardware De La Computadora Achronix Speedster22i HD1000 Development Kit User Guide Manual de usuario
(69 paginas)
(69 paginas)
Hardware De La Computadora Achronix Speedster22i HD1000 Development Kit Quickstart Gui Manual de usuario
(2 paginas)
(2 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.054 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales