Achronix Speedster22i User Macro Guide Manual de usuario descargar pdf (Pagina 214)

PLL/DLL Clock Generators ACX_CLKGEN

Speedster Macro Cell Library

www.achronix.com PAGE 197

Figure 9-3: Serial Control Bus Read Operation

Figure 9-4: Serial Control Bus Write Operation

Control Status Registers (CSR) Register Description

Table 9-4: Control Status Registers (CSR) Description

{A16,A15}

ick_dspll_sif_clk

ick_sbus_req

ick_sbus_data[1:0] {A0,1’b0} {A2,A1} {A4,A3}

ock_sbus_ack

ock_sbus_data[1:0]

{D1,D0} {D3,D2} {D31,D30}{D29,D28}

{A16,A15}

ick_dspll_sif_clk

ick_sbus_req

ick_sbus_data[1:0] {A0,1’b1} {A2,A1}

ock_sbus_ack

{D1,D0} {D3,D2} {D31,D30}

CSR NAME Addr. Bit Type Initial Value Description

CSR_ADDR_USER_RESERVE_00 8’h00 0 in/out Reserved Not Used

1 in/out Reserved Not Used

2 in/out Reserved Not Used

3 in/out Reserved Not Used

4 in/out Reserved Not Used

5 in/out Reserved Not Used

6 in/out Reserved Not Used

7 in/out Reserved Not Used

CSR_ADDR_SYNTHOUT0 8’h01 0 in/out outdiv0[0] Clkout[0] Output Divider Divisor bit 0

1 in/out outdiv0[1] Clkout[0] Output Divider Divisor bit 1

2 in/out outdiv0[2] Clkout[0] Output Divider Divisor bit 2

3 in/out outdiv0[3] Clkout[0] Output Divider Divisor bit 3

4 in/out outdiv0[4] Clkout[0] Output Divider Divisor bit 4

5 in/out outdiv0[5] Clkout[0] Output Divider Divisor bit 5

6 in/out phase_inc[0] Increments phase of synthesizer clock out-

put by 1/8th of1 period on rising transition

7 in/out clken_out0 Enable for Clkout[0] Output Synthesizer

1 2 ... 209 210 211 212 213 214 215 216 217 218 219 ... 223 224

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Achronix Speedster22i User Macro Guide Manual de usuario Pagina 214