Achronix Speedster22i User Macro Guide Manual de usuario descargar pdf (Pagina 58)

I/O Cells OPAD_DIFFD2

Speedster Macro Cell Library

www.achronix.com PAGE 41

Table 1-47: Parameters

Parameter Defined Values Default Value

locationp

locationn

iostandard “LVCMOS18”

drive

rstmode

rstvalue

slew

keepmode

hysteresis

invert_out “on”, “off ” “off ”

open_drain “true”, “false” “false”

pvt_comp “none”, “own” “none”

odt “off ”, “on” “off ”

termination “50”, “60”, “75”, “100”

, “120”, “240” “50”

Figure 1-21: OP

AD_DIFFD2 Output Timing Diagram (assumes data_en = 1’b1)

Verilog Instantiation Template

OPAD_D2 #(.locationp(""),

.locationn(""),

.iostandard("LVCMOS18"),

.drive("16"),

.rstmode("async"),

.rstvalue("low"),

.slew("slow"),

.open_drain("false"),

.invert_out("off"),

.pvt_comp("none"))

instance_name (.pad(user_pad), .dina(user_dina), .dinb(user_dinb),

.data_en(user_data_en)

, .rstn(user_rstn), .clk(user_clk));

“<pad_location>” ““

“<padn_location>” ““

See Table1‐1

"2", "4", "6", "8", "12", "16" "16"

“sync”, “async” “async”

“low”, “high” “low”

“fast”, “slow” “slow”

"pullup", "pulldown", "none" “none”

"none", "schmitt" “none”

clk

dina

dinb

pad

padn

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 223 224

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