Achronix Speedster22i User Macro Guide Manual de usuario descargar pdf (Pagina 46)

I/O Cells OPAD_D

Speedster Macro Cell Library

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OPAD_D

Registered Output Pad with Asynchronous or Synchronous Set/Reset

rstn

din pad

clk

data_en

OPAD_D

Figure 1-15: OPAD_D Logic Symbol

OPAD_Disaregisteredoutputpa

d.Theoutputregisterisclockedontherisingedgeofthe

clock. Driving rstn low performs an asynchronous initialization of the output register if the

rstmode parameter is set to async and performs a sychronous initialization of the output

nc.Thevalueinitializedintotheoutputregisteris

determinedbythevalueoftherstvalueparameter.

Table 1-33: Ports

Name Type Description

pad Device output pad.

din

Positive-edge based data input. Data

is clocked into the output register

upon the rising edge of the clk input, and is driven to the pad.

data_en

Output Register Clock Enable. A

high value on data_en enables the Out-

put Register to clock the din input to the

output at the next rising edge of

the clock. A low value on data_en allows the Output Register to retain its

current value.

rstn

Output Register Reset. If the

value of the rstmode parameter is “async”, a

low value on the rstn input performs an asynchronous initialization of the

Output Register. If the value of the rstmode parameter is “sync”, a low value

on the rstn input performs a synchronous initialization of the Output Reg-

ister on the next rising edge of the clock

. The value initialized into the Out-

put Register is determined by the value of the rstvalue parameter.

clk Output Register Clock input.

output

input

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 223 224

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Achronix Speedster22i User Macro Guide Manual de usuario Pagina 46