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Achronix Speedster22i HD1000 Development Kit User Guide Manual de usuario Pagina 41

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UG034, July 1, 2014
41
you with an ACE template to correctly allocate these IO pins, Bank East-South (Byte 0 – 12), for
your designs. Appendix A details these pins and their connections to the SO-DIMM socket.
Note: You will need to buy the memory separately. The kit does not ship with the memory.
One DDR3 Device (U21)
You can use the 2 Gb, Micron MT41J128M16JT-093, DDR3 memory device soldered on the
board. The HD1000 drives the memory signals using dedicated GPIOs. Although you may
repurpose these IO pins, Bank West-Centre (Byte 0 – 12), on your designs, you must maintain
the allocation shown in Table 13 to use the device provided on the board.
Note: Do not reallocate these Ios on the ACX-BRD-HD1000-100G development board. This could
lead to unexpected behavior.
Note: The IO mapping on the ACX-BRD-HD1000-100G development board has NOT been
implemented to work with the hardened DDR3 controller IP. A soft DDR3 controller implementation
is needed in the FPGA fabric to get the IO mapping needed to work with the discrete DDR3 device.
Table 13: ACX-BRD-HD1000-100G Memory Interfaces – DDR3
Signal Name
Pin on HD1000 (U33)
Pin on MT41J128M16JT (U21)
DDR3_DQ0
BA2
E3
DDR3_DQ1
AV1
F7
DDR3_DQ2
AW1
F2
DDR3_DQ3
BB2
F8
DDR3_DQ4
BC1
H3
DDR3_DQ5
AU1
H8
DDR3_DQ6
BB1
G2
DDR3_DQ7
BC2
H7
DDR3_DQ8
AH14
D7
DDR3_DQ9
AG14
C3
DDR3_DQ10
AJ13
C8
DDR3_DQ11
AC13
C2
DDR3_DQ12
AJ14
A7
DDR3_DQ13
AE14
A2
DDR3_DQ14
AH13
B8
DDR3_DQ15
AE13
A3
DDR3_A0
AT2
N3
DDR3_A1
AF2
P7
DDR3_A2
AK2
P3
DDR3_A3
AM1
N2
DDR3_A4
AC2
P8
DDR3_A5
AP2
P2
DDR3_A6
AE1
R8
DDR3_A7
AL1
R2
DDR3_A8
AN1
T8
DDR3_A9
AT1
R3
DDR3_A10
AC1
L7
DDR3_A11
AG2
R7
DDR3_A12
AJ1
N7
DDR3_A13
AK1
T3
DDR3_BA0
AM2
M2
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