
UG034, July 1, 2014
Appendix D – Revision History
The following table lists the revision history of this document.
Initial Achronix release.
Updated crystal oscillator component numbers.
Put in more component numbers in figures. Updated
Interlaken tables.
Minor syntactical updates.
Table to show clock synth switches and output freq. Updated
table 22 for pad2_clk_bank_se. 72Mb QDRII+ @ 633MHz.
Minor corrections based on feedback.
Updates for the clock synthesizer and other corrections.
Removed heat sink from BOM.
Note for DDR3 discrete device. Corrected Figure 1.
Corrected SerDes SMA location in Figure 9.
Corrected oscillator Y3 pin mapping on page 51.
Corrected Digilent, Interlaken, FMC, QDRII+ and RLDRAM3
mappings.
Updated FMC and RLDRAM3 mappings.
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