Achronix Speedster22i HD1000 Development Kit User Guide Manual de usuario descargar pdf (Pagina 66)

66 UG034, July 1, 2014

Jumper

Implementation

Connected

Pins

Function

J46

Surface Mount

Resistor

Selects VDDL_REG

0.75V-1.2V

0.75V

1.0V

1.2V

J51

Surface Mount

Resistor

Selects VDD_BRAM_FB

0.75V-1.2V

0.75V

1.0V

1.2V

J53

Surface Mount

Resistor

None

1 & 2

Selects V3P3

2 & 3

Selects VBB_INLKN1

Note: ‘*’ denotes default setting.

Switches

Table 29: Switches and their Functions

Switch

Function

Connection

Through

Comment

SW4

Generates RUN signals

U64

Drives ON_OFF_SW

HD1000 reset*

U76

Drives FPGA_RESET1

* Usage of HD1000 reset requires a reset signal in the design to be routed to the IO

corresponding to the switch, which is pad2_clk_bank_sw = P17.

Table 30: DIP switches and their Functions

Switch

Function

Connection

Position

Through

Signal

SW13

PLL/Bypass mode

U102

E_VCCO_SEL_2

Output divider value

E_NA2_2

Output divider value

E_NA1_2

Output divider value

E_NA0_2

Output divider value

E_NB2_2

Output divider value

E_NB1_2

Output divider value

E_NB0_2

Clock divider input

E_M8_2

SW12

Clock divider input

E_M7_2

Clock divider input

E_M6_2

Clock divider input

E_M5_2

Clock divider input

E_M4_2

Clock divider input

E_M3_2

Clock divider input

E_M2_2

Clock divider input

E_M1_2

Clock divider input

E_M0_2

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